The invention relates to an embedded testing circuit for testing a dual port memory and to a method for testing a dual port memory.
A dual port memory is accessible through two separate ports. A conventional dual port random access memory consists of two ports which are designed to operate independently, giving flexibility of doing read and write operations from both ports simultaneously. However, it is prohibited to simultaneously write different values to the same address of the random access memory from both ports.
The testing of a dual port memory can be done by simply performing sequential read and write operations from both ports. To guarantee functionality of a dual port random access memory it is necessary to test whether the dual port memory is operable in any situation, and in particular, it is essential to do simultaneously read and write operations from both ports during the testing to ensure the functionality and performance of the dual port random access memory as it is required by the specification.
DRAMs and SRAMs differ little in their application. DRAMs are distinguished from SRAMs in that no bistable electronic circuits internal to the storage cell maintaining the information are provided. In DRAMs, the information is stored dynamically as charge on a capacitor. SRAMs maintain their bi-stability as long as power is supplied by a cross coupled pair of inverters within each memory cell. Two additional transistors serve to access internal nodes for reading and writing. In most designs, the storage cells are CMOS with two P-channel and four N-channel field effect transistors.
A dual port memory has an integrated memory cell array consisting of a plurality of memory cells arranged in a matrix and accessible via word lines and bit lines.
FIG. 1 shows a bit line structure in a dual port memory cell. The bit line BLA of port A, the bit lines BLB of port B and the inverted bit lines of both ports, BLB and BLBA are Shielded from each other by a line on a predetermined potential, such as VDD or ground, to reduce capacitive coupling between the bit lines. This is in particular important, since the size of the memory cells which are integrated is continuously shrinking. When data in one memory cell is inverted to that of another memory cell of the same column, both memory cells are accessed simultaneously from both ports, A, B a voltage difference between the bit line pair is reduced resulting in a slow read/write operation.
Testing of a dual port memory with an embedded testing circuit has been described in U.S. Pat. No. 5,579,322 as shown in FIG. 2. As can be seen from FIG. 2, the testing circuit is embedded in a conventional dual port memory RAM having two ports A, B. The testing circuit comprises a first group of scan registers (B1) and consists of serially connected plural stages of scan registers provided for each port at the address input side of the dual port memory. The testing circuit comprises an address generation circuit selectively supplying a predetermined address data pattern from one port side and the inverted address data pattern to the other port side. Accordingly, the address inputs to both ports A, B have a bit inverse relationship to each other at all times and consequently, the address inputs on both ports will not become identical at any time.
A second group of scan registers B2 is formed of serially connected plural stages of scan registers provided on each port at the data input side of the dual port memory RAM. The data generation circuit is provided for selectively supplying a predetermined test data pattern or the inverted test data pattern passed through one port side of the first group of scan registers to the second group of scan registers. Since the data written from port A and the data written form port B are always in a inverse relationship to each other, it is possible to write and read a logical “0” and a logical “1” from all addresses or from both ports, A and B.
At the data output side of the dual port RAM and the data input side there are arranged also three scan registers which are serially connected at their respective boards as a third group of scan registers corresponding to the output node.
Since the address input and the two ports, A, B have a bit inverse relationship at all times for all addresses it is not ensured that simultaneously a read/write operation is happening at the same column. Furthermore, a simultaneous selection of two adjacent rows for all memory cells is not possible.
FIG. 3 shows a test data sequence for testing the dual port RAM according to the state of the art as shown in FIG. 2. The table FIG. 3 shows 16 iteration steps i for applying a four bit test address A (i).
A disadvantage of the embedded testing circuit according to the state of the art as described in U.S. Pat. No. 5,579,322 as shown in FIG. 2 applying the test data sequence as shown in FIG. 3 is, that the dual port memory RAM is not tested in a worst case scenario, i. e. at a worst possible operating frequency. The worst operation scenario for a dual port memory is fulfilled if three conditions are met simultaneously. Because of the coupling capacitance between different memory cells which are arranged in rows and columns, the worst operation scenario resulting in the lowest operating frequency of the RAM is given, when a first condition is met, i. e. when at the same time the same columns from both ports, A, B are selected. As a second condition, two adjacent rows used in the memory cell array are activated simultaneously. And finally, as a third condition, the worst case scenario is fulfilled when at the same time an inverted test data pattern is generated for both ports, A, B.
By the embedded testing circuit according to the state of the art as described in U.S. Pat. No. 5,579,322 testing is not performed for adjacent rows and memory cells at any time. For instance, when proceeding from the iteration step 1 to the iteration step 2, as shown in the table of FIG. 3, the applied address is changed from “1000” to “1100”. In iteration step 1 the address applied to port A is “1000” and the address applied to port B is the inverted bit pattern “0111” so that in this iteration step adjacent rows in the memory cell array are addressed. However, in iteration step 2, the address applied to port A is “1100” and the address applied to port B is the inverted bit pattern “0011” addressing distant rows in the memory cell array. Accordingly, in iteration step 2, the memory cells are not adjacent, i. e. distant rows are addressed and tested. Therefore, the embedded testing circuit of U.S. Pat. No. 5,579,322 is not testing a functionality of the dual port RAM at the slowest possible operating frequency.
Accordingly, it is an object of the present invention to provide an embedded testing circuit for testing the functionality of a dual port RAM at its lowest possible operating frequency as well as a method for testing such a dual port memory.